A SystemVerilog-UVM Methodology for the Design, Simulation and Verification of Complex Readout Chips in High Energy Physics Applications

The adoption of a system-level simulation environment based on standard methodologies is a valuable solution to handle system complexity and achieve best design optimization. This work is focused on the implementation of such a platform for High Energy Physics (HEP) applications, i.e. for next generation pixel detector readout chips in the framework of the RD53 collaboration. The generic and re-usable environment is capable of verifying different designs in an automated fashion under a wide and flexible stimuli space; it can also be used at different stages of the design process, from initial architecture optimization to final design verification.