Pixel Chip Architecture Optimization Based on a Simplified Statistical and Analytical Model

The technical challenges related to increased collision rates of the LHC will significantly affect detector electronics design. Efficient hit processing is achieved in pixel detectors by grouping pixels in regions, which share buffering logic. We present an approach to determine an optimized sharing strategy between pixels, depending on the shape of clustered hits in the detector. Simple statistical models of such shapes have been developed with respect to the position in the detector. The buffering performance of different pixel region configurations has been compared, showing significant improvement from architectures that do not feature pixel grouping.