A UVM simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

TheoperatingconditionsoftheHighLuminosityupgradeoftheLargeHadronCollider areverydemandingforthedesignofnextgenerationhybridpixelreadoutchipsintermsofparticle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidatedtoolsandmethodologies,suchasSystemVerilogandtheUniversalVerification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guidedthedesignofdigitalarchitectures,optimizedforprocessingandbufferingveryhighparticle rates, and secondly how it has been reused for the functional verification of the first large scale demonstratorchipdesignedbythecollaboration,whichhasrecentlybeensubmitted.