The CMS central tracker will use clock and trigger signals derived from the general Timing and Trigger Control (TTC) system developed within the RD-12 project. These signals are transmitted encoded in a 40 MHz square wave that simply presents a missing pulse when a trigger occurs. This paper describes the design of a dedicated low jitter PLL-Delay ASIC optimized for this application. Design requirements and preliminary simulation results are reported. Special emphasis is put into the optimization of several blocks of the PLL; furthermore the description of a mathematical model used for the optimization of the circuit is detailed.
A PLL-Delay ASIC for Clock Recovery and Trigger Distribution in the CMS tracke
PLACIDI, Pisana;
1997
Abstract
The CMS central tracker will use clock and trigger signals derived from the general Timing and Trigger Control (TTC) system developed within the RD-12 project. These signals are transmitted encoded in a 40 MHz square wave that simply presents a missing pulse when a trigger occurs. This paper describes the design of a dedicated low jitter PLL-Delay ASIC optimized for this application. Design requirements and preliminary simulation results are reported. Special emphasis is put into the optimization of several blocks of the PLL; furthermore the description of a mathematical model used for the optimization of the circuit is detailed.File in questo prodotto:
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