This work aims at exploring and validating the adoption of standard fabrication processes for the realization of CMOS active pixel sensor, for particle detection purposes. The goal is to implement a single-chip, complete radiation sensor system, including on a CMOS IC the sensitive devices, read-out and signal processing circuits. The possibility of including versatile and performing circuitry allows for the evaluation of innovative active pixel architectures, different read-out strategies, and complex data management algorithms. A prototype chip (RAPS01) based on these principles has been already fabricated, and a complete chip characterization has been carried out; in particular, the evaluation of the sensitivity of the sensor response on the actual operating conditions was estimated, as well as uniformity response analysis. Optimization and tailoring of the sensor structures for specific applications are being evaluated in the design of the next generation chip (RAPS02). In particular, sparse read-out approach and power consumption are considered, introducing some circuit improvement, and discussing the organization and design of a new architecture. Basic features of the new chip includes: digitally configurable readout, power-switching techniques, fault-tolerant circuitry, multi-mode access (i.e., either sparse of line-scan readout). Thanks to the intrinsic flexibility of CMOS design, perspective application different from HEP experiments, can be evaluated as well.

Advances in radiation active pixel sensors (RAPS) architectures

PLACIDI, Pisana;PASSERI, Daniele;
2004

Abstract

This work aims at exploring and validating the adoption of standard fabrication processes for the realization of CMOS active pixel sensor, for particle detection purposes. The goal is to implement a single-chip, complete radiation sensor system, including on a CMOS IC the sensitive devices, read-out and signal processing circuits. The possibility of including versatile and performing circuitry allows for the evaluation of innovative active pixel architectures, different read-out strategies, and complex data management algorithms. A prototype chip (RAPS01) based on these principles has been already fabricated, and a complete chip characterization has been carried out; in particular, the evaluation of the sensitivity of the sensor response on the actual operating conditions was estimated, as well as uniformity response analysis. Optimization and tailoring of the sensor structures for specific applications are being evaluated in the design of the next generation chip (RAPS02). In particular, sparse read-out approach and power consumption are considered, introducing some circuit improvement, and discussing the organization and design of a new architecture. Basic features of the new chip includes: digitally configurable readout, power-switching techniques, fault-tolerant circuitry, multi-mode access (i.e., either sparse of line-scan readout). Thanks to the intrinsic flexibility of CMOS design, perspective application different from HEP experiments, can be evaluated as well.
2004
9780780387003
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11391/170279
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