In this paper we present a novel implementation of the JPWL standard on a DSP device, targeted to the protection of HD video streams at 50 Mbit/s. Several investigations on computational cost have been carried out in order to find the parts that had to be optimized for DSP. The result is an implementation that uses tailored instructions for operation on Galois Field and Enhanced Direct Memory Access (EDMA) for interleaving.
A real-time, DSP-based JPWL implementation for wireless high-definition video transmission
FIORUCCI, FEDERICO;BARUFFA, Giuseppe;MICANTI, PAOLO;FRESCURA, Fabrizio
2011
Abstract
In this paper we present a novel implementation of the JPWL standard on a DSP device, targeted to the protection of HD video streams at 50 Mbit/s. Several investigations on computational cost have been carried out in order to find the parts that had to be optimized for DSP. The result is an implementation that uses tailored instructions for operation on Galois Field and Enhanced Direct Memory Access (EDMA) for interleaving.File in questo prodotto:
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